DSP: Pushing the packets
The 17x17mm box at the left is not just a typographical decoration. It is the size of a new digital signal processor (DSP) chip created by Motorola, based on its Star*Core Alliance joint DSP development venture with Lucent Technologies.
The communications infrastructure world is not only getting smaller, it’s getting faster. Motorola’s MSC8101 processor, based on the joint core design, can handle nearly 25 times as many instructions as DSP chips of just a few years ago-that is, about 1,200 million instructions-per second.
Fifteen years ago, wireless was still an analog world-it still is, justifiably, for some applications. But digital, enabled by DSPs, will dominate communications technology in the coming decade. DSPs can decode ID numbers and paging messages into alphanumeric characters for LCDs. DSP benefits have included reduced bandwidth and voice compression; error-correction; noise cancelation and other filtering; analog-to-digital conversion (modulation and demodulation); voice and data scrambling; and speedier, compact modems.
Twenty years ago, analog circuitry modems had a top speed of 1,200bps and were only slightly smaller than a shoe box. Digital signal processors were introduced that used mathematical algorithms to perform consistent modulations-with increasing speed. (Modem speed accelerated from 1,200bps to 14,400bps to 56,000bps in just a few years.) Now, modems are the size of a credit card.
High-end DSPs can even perform some of the functions of a conventional central processing unit (CPU). DSPs’ affinity for Internet protocol (IP) networks and for speech-recognition and language-processing routines will make them even more indispensable as communications technologies converge in the coming years.
A computer within a computer DSPs are basically special-purpose microprocessor chips that execute instructions. They specialize in applications such as integer/floating point performance, on-chip peripherals, special assembly-language instructions and parallel access to memory. What that “nerd talk” means to telecommunications is that DSPs rapidly perform repetitive tasks such as compression, packetizing and modulation of the human voice. DSP speed is measured in millions of instructions per second (MIPS).
DSP development reflects “Moore’s Law” of escalating performance, and cost and capabilities have become inversely related. The performance of general-purpose DSP chips doubles about every three years, while costs halve over the same time.
Voice compression is a prime application for DSPs. Voice travels on circuit-switched networks at 64,000bps. DSP algorithms compress voice so that it can be sent at slower speeds. Slower is better because it optimizes the use of bandwidth. Therefore, the bandwidth, or capacity, required to transmit voice over packet networks drops from 64,000bps to around 12,000bps (including headers). The acquired speeds of DSPs now make voice and video achievable over IP networks.
Not-so-strange bedfellows Industry analysts estimate the worldwide market for DSPs at $3 billion. The plurality of that market, about 45%, lies in the field of communications. With a 33% growth rate, the global market may reach $14 billion by 2002. This makes the partnership of Motorola and Lucent opportune-if not inevitable. The strategic alliance the two companies forged in mid-1998 yielded a first-generation core in less than one year, instead of three. The companies are also cross-licensing existing DSP architectures.
David Baczewski, strategic marketing manager for Motorola’s Wireless Infrastructure Systems Division, Austin, TX, said the Star*Core Alliance joint development center (JDC) in Atlanta teams Motorola and Lucent employees with a mandate to develop DSP core technology. Each company then takes that core and adds its own peripheral sets to create products. The MSC8101, unveiled in the fall of 1999 and illustrated on the facing page, is the first Motorola DSP based on the joint core design.
“From a historical perspective, both companies have deviated from the practice of each individually going out and developing its own core technology. This is a pretty common methodology, to develop a DSP product, to develop basically the core, then wrap a set of peripherals around it. We’ve deviated with Star*Core in that both Motorola and Lucent are working together on that core technology,” Baczewski said.
The reason is simple: A new core technology requires a substantial investment in resources and a lengthy time to market. By pooling their significant resources, the companies can create new processors quicker and concentrate more on end-products.
“Not only that, from a third-party perspective, a tools perspective and an applications perspective, you’ve got a common core technology that you can write code for. So you’ve code compatibility and a lot of commonality in the tools, specifically in the compiler,” Baczewski said. The ability to develop software for the core in more contemporary and universally used programming languages should speed the time to market for applications, he added.
“In the past, DSP technology was based mostly on assembly language, and we’re now moving to a phase in the history of DSPs where you really want to do everything in ‘C’ or ‘C++.’ The ‘C’ compilibility is absolutely a requirement, and efficiency is kind of the ‘Holy Grail’-what everybody’s after. That, historically, has not been the case. But now, with the Star*Core, we feel that we’ve got a very good story from the ‘C’ compiler standpoint,” Baczewski said.
The first Star*Core DSP, on which Motorola’s MSC8101 is based, is designated as the SC140 (Star*Core 100 family; “4” indicates the number of arithmetic logic units [ALUs] on the device).
“One of the unique things about this core technology is the fact that the architecture is ‘scalable,'” Baczewski said. “So I can do an ‘SC110,’ with one ALU, all the way up to an ‘SC180,’ with eight ALUs.” This scalability will provide the two developers with flexibility and longevity in the market, he added.
The Atlanta think-tank is already planning the next generation of core families, SC200.
“One of the objectives is to maintain backward compatibility and consistency with the development tools” (within the Star*Core family),” Baczewski said. “At some point, you have to break the chain, and this is a paradigm shift in terms of architecture and performance. With any new processor technology, you have to make a break and move on to the next generation.”
Speed, performance, low power consumption and compilibility were the goals for the core development, he said. To take an application, compile and get to market quickly, while building an efficient code that can make good use of external resources.
“So, the idea behind this, really, was an architecture that would support everything from infrastructure down to terminals or subscriber applications,” Baczewski said. “The 8101 [MSC8101], which is focused on infrastructure, is at the high end. The power consumption for that device is very low, about 0.5W for the entire device. It’s delivering 1,200 million MACs (1.2 billion multiply-accumulate operations, roughly equivalent to 3 billion instructions) per second.” Baczewski noted that some developers now refer to MIPs as “meaningless indication of processor speed,” because it doesn’t necessarily indicate operations performance.
“The ultimate benchmark, in terms of performance, is the application, and it’s really how many channels you can do with the device,” he said.
Third-party embedded communications software written for the Star*Core design is already under development for cellular, PCS, paging and base station equipment. This includes software for GSM, CDMA and TDMA vocoders, hybrid echo cancelers and modems.
The prime applications target for this new generation of DSPs will be wireless infrastructure, next-generation (2.5G and 3G) wireless; IP telephony, including voice/fax modem video/IP gateways; asynchronous transfer mode (ATM) edge carrier switches handling voice/fax modem/video; modem banks; hybrid modems; and noise-cancelation technologies.
Baczewski said Motorola brought over technology from its 56300 product family where it pioneered the capability to add coprocessors within the device itself; not only to have a core, but to add, internal to the device, specialized coprocessors to do specific functions.
“One of those specific functions is filtering, so we have something called an ‘enhanced filter coprocessor’ that we’ve borrowed from the 56300 family and incorporated into the 8101. So the 8101, along with its core, has a separate MAC unit, sitting off to the side, that does filtering operations, which can be a variety of things, including echo cancelation,” Baczewski said.
Advances in DSP technology will not only mean newer, faster applications and devices, but modifications to existing systems. Infrastructure equipment in the field is rarely pulled out and replaced wholesale. Replaceable cards for existing systems will increase functionality to support new features and wireless standards, cost reductions and replacement of older technology.
Modulation formats also stand to benefit from new speech-coding techniques and algorithms. For GSM, for example, Motorola developed the “adaptive multirate” (AMR) speech coder.
“What we’re seeing in next-generation systems is that the types of algorithms are becoming quite a bit more complex, maybe in an order of magnitude, in some cases, than today’s algorithms. So, what we’re finding is that they just need more MIPS to be able to do these sort of things. On top of that, there’s the ability to move around large pieces of data and to be able to handle multichannel applications running on a single device,” Baczewski said.
“One of the problems that they’re facing with these new protocols, with the higher bandwidth, higher data rates, is the ability to move large chunks of data in and out of the system,” he said. The advantage of the new DSPs on the network side will be to directly connect to a series of various network connections: E1/T1 or E3/T3, Utopia bus, ATM backplanes or 100Mbit Ethernet.
“So you’ve got on that side a very wide pipe and high-performance capabilities, and on the system side you have the PowerPC bus. Once you’ve pulled the data off the pipeline, you want to send it back to rest of the system. Again you need a pretty wide interface bus, and PowerPC, a 100MHz, 64-bit bus, is a pretty high-performance bus that is able to do that. So it’s a combination of MIPs, or MACs, whichever-basically raw DSP performance-in combination with high-bandwidth bus interfaces.”
Baczewski sees a “paradigm shift” in how systems are being built, moving from a centralized architecture with a single controller handling multiple DSPs to a distributed network with the ability for the DSP to extract the payload data right off the network and off-load some of the work that has been traditionally handled by the controller.
“The other area is a shift from circuit-switched networks to packet-switched networks,” he said. “If you look at voice today, it’s primarily circuit-switched. The new focus and the buzzword in the industry is ‘voice-over IP,’ and the ability to handle voice over a packetized network. To be able to do that you need a wide-bandwidth type of device hooked directly into that network.”
The challenge, Baczewski said, will be to match the quality of service of a circuit-switched network with a packet-switched network.
OEMs will have new DSP chips and software available to apply to production before the end of this year. The potential for innovations in wireless subscriber and infrastructure equipment in the next few years is enormous.
